Automated analog radio-frequency (RF) circuit design remains challenging due to nonlinear device behavior, sparse feasible regions, expensive simulation-based evaluations, and discrete constraints imposed by process design kits (PDKs). This work presents a validity-gated multi-objective Bayesian optimization (MOBO) framework for Complementary Metal-Oxide-Semiconductor (CMOS) low-noise amplifier (LNA) design over a mixed discrete-continuous search space defined by foundry PDK constraints. The approach employs a physics-informed parameter initialization combined with Latin hypercube sampling (LHS) to construct an initial dataset that ensures circuit-level feasibility while maintaining device operation within bounded regions. Discrete PDK elements, including quantized inductor selections and constrained device dimensions, are directly embedded in the optimization search space. A Gaussian process (GP) surrogate model, combined with a validity-gated acquisition strategy, then guides the search by filtering out infeasible evaluations and improving simulation efficiency throughout the optimization process. The framework is validated on a 2.4 GHz current reuse cascode LNA designed in Cadence Virtuoso and simulated using Spectre in a Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm CMOS process. Under a fixed budget of 190 simulations (120 LHS + 70 MOBO), the method achieves a 62% reduction in power consumption and a 10.7 dB improvement in the input third-order intercept point (IIP3) @ 2.4 GHz relative to a handcrafted expert baseline, reflecting a Pdc–noise figure (NF)–IIP3 Pareto trade-off. The minimum-power Pareto design exhibits a modest NF increase (2.19 dB vs 1.98 dB for the manual baseline), while NF-optimized Pareto solutions achieve NF as low as 1.84 dB. The dominated hypervolume expands by 105% over LHS initialization alone, and valid simulation yield improves from 47.5% to 95.7% under guided optimization. These results demonstrate that physics-informed initialization combined with validity-gated Bayesian optimization enables efficient exploration of constrained, mixed-variable CMOS RF design spaces, achieving expert-level performance without manual heuristic tuning.